FPGA Design Engineer Interview Question Part-1

Hey guys hope you all are doing very great. Wishing you all a very Happy Diwali , Happy Gobardhan Puja ,Happy Bhai Duj and Happy Chatt Puja. .Guys this the first part of FPGA Design Engineer interview questions asked by various product and service based companies .

The overall interview process is divided into 2 parts:

The first part is Digital Logic design or Digital electronics concepts: – Almost all the companies select the candidates on the basis of the knowledge of digital fundamentals including the topics (Basics of logic gates , Number Systems , Combinational Logic Circuits , Sequential logic circuits , Memories ,FSM and etc). A good foundation of digital electronics is very important as it the fundamental building block of VLSI Design.

Most of the job profiles in the semiconductor industry look for strong knowledge in digital concepts and its application . A good knowledge of digital electronics will give you the confidence of getting into the VLSI Industry.

  1. What is state machine ? What are the different types ? Explain the difference ? which one is most preferable ?
  2. How many 4X1 mux are required for the design of 128×1 mux?
  3. Which flip flop is basically used for the designing of shift register and why?
  4. One Boolean expression will be given and you have to minimize the expression? Mostly they give you the sum and carry expressions of full adder. Note: Always check the order of the variable while solving this question.
  5. What is set-up and Hold time? Explain?
  6. Which logic gates are called universal logic gates and why?
  7. Design a sequence detector which can detect the sequence (1101)2.

The second part of the interview was based on verilog or VHDL concepts. Most of the companies asks questions from verilog concepts.

Here are the questions asked from Verilog:

  1. Explain Blocking and Nonblocking assignment.
  2. Which assignment will be used for the designing of combinational logic circuits?
  3. Write a verilog code for 4×1 multiplexer with blocking assignment and nonblocking assignment and comment upon the output result.
  4. What is the difference between Reg and Wire datatype?
  5. Explain the difference between FPGA design flow and ASIC design flow.
  6. Some names of FPGA vendors.
  7. In which sectors or Applications FPGA’s are used mostly and why?
  8. What is the difference between Task and Function?
  9. Write a task by taking two integer variable , which will detect the bigger number when called.
  10. There are 8 identical balls among which one is defective . Explain how many minimum number of iterations are required to detect defective ball. (The defective ball will be having either lesser or higher weight then other balls).

Guys you can go through these questions and definitely it will be helpful in cracking the VLSI job in the field of FPGA Design. These questions are asked to a candidate having more then 4 years of relevant experience in FPGA Design. It will also be helpful for any fresher candidate.

You guys can get the answers of these questions by your own but I will be preparing the answers for these questionnaire in upcoming articles.

Thank you very much guys . . Happy Learning . .

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