Hey guys hope you all are doing very great. Today I will be posting a set of questions which has been asked to one of our active reader for the role of Design and Verification engineer.
The overall interview process is divided into 3 parts:
The first part is Digital Logic design or Digital electronics concepts:
- What is K – Map and why do we use it?
- What are the basic logic gates?
- What are the universal logic gates?
- What is SOP and POS?
- What is Minterm and Maxterm?
- What is the difference between Latch and Flipflop?
- What is Fan-in and Fan-out?
- What is setup time and hold time?
The Second part of the interview was based on System Verilog. It depends on the interviewer which topic they choose for the interview. If they are looking for a candidate mostly for design they may definitely ask questions from Verilog. If they want the candidate for verification domain they may ask question from System Verilog and UVM (Universal Verification Methodology).
Here are the questions asked from System Verilog:
- What is the difference among Reg , Wire , Logic?
- What is the difference between packed and unpacked array? with example.
- What is the difference between struct and union?
- How to declare a dynamic array and how to add additional memory with the existing created memories ?
- What are the different types of constraints?
- What is the difference between Soft Constraint and Hard Constraint?
- What is callback?
- What is forward declaration?
- Where do we write assertions?
Questions asked from UVM domain for verification:
- What is the difference between sequence and sequence item?
- what is sequencer ?
- What is TLM?
Guys you can go through these questions and definitely it will be helpful in cracking the VLSI job in the field of design and verification. These questions are asked to a candidate with 5 years of experience in Design and Verification. It will also be helpful for any fresher candidate.
You guys can get the answers of these questions by your own but I will be preparing the answers for these questionnaire in my next article.
Thank you very much guys . . Happy Learning . .
Click Here for Design and Verification Interview Question Part-2