Design Verification Interview Question Part-2

Hey guys hope you all are doing very great. This the part 2 of Design verification Interview question .Today I will be posting a set of questions which has been asked to one of our active reader for the role of Design and Verification engineer for the very renowned company “Wipro”. Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions. Wipro is considered as one of the best workplace for the employees working in various areas of corporate.

The overall interview process is divided into 4 parts:

The first part is Digital Logic design or Digital electronics concepts: – Almost all the companies select the candidates on the basis of the knowledge of digital fundamentals including the topics (Basics of logic gates , Number Systems , Combinational Logic Circuits , Sequential logic circuits , Memories ,FSM and etc). A good foundation of digital electronics is very important as it the fundamental building block of VLSI Design.

Most of the job profiles in the semiconductor industry look for strong knowledge in digital concepts and its application . A good knowledge of digital electronics will give you the confidence of getting into the VLSI Industry.

  1. How to design an AND gate using a 2×1 multiplexer?
  2. Can a 2X1 multiplexer be considered as universal circuit? if yes how?
  3. What are the universal logic gates?
  4. Explain the encoders and decoders with an example.
  5. What is the difference between Latch and Flipflop?
  6. What is setup time and hold time?
  7. What is FSM? What are the types? which one is preferred?

The second part of the interview was based on verilog or VHDL concepts. Most of the companies asks questions from verilog concepts.

Here are the questions asked from Verilog:

  1. Write a verilog code for Half adder.
  2. Write a verilog code for bidirectional shift register? defining SISO , SIPO , PISO , PIPO as parameter.
  3. Which tool do you use for the design and simulation?
  4. Any idea about FPGA?

The third part of the interview was based on System Verilog.

Here are the questions asked from System Verilog:

  1. What is the difference among Reg , Wire , Logic?
  2. What is the difference between function and task?
  3. Can I write task inside function?
  4. Can I write task inside function with zero time delay?
  5. What is polymorphism ? Explain with a code.
  6. What are the different types of constraints?
  7. Take two integer variable X and Y . Write a constraint in such a way that both X and Y must generate random numbers between 2 to 10 with a condition.(If X = 2 then Y = 6).
  8. What is race condition and how to avoid this. (System Verilog).
  9. What is the need of assertions?
  10. What is virtual interface?
  11. What is mailbox?

Questions asked from UVM domain for verification:

  1. What is the difference between sequence and sequence item?
  2. What are the different UVM phases?
  3. Which UVM phase contains delay?
  4. what is sequencer ?
  5. What is TLM?
  6. What is UVM factory?
  7. How does a sequencer communicate with the driver ?
  8. How the UVM TB architecture is different from SV TB architecture?

They also ask you few of the questions from on-chip communication protocols. Any knowledge of AXI , APB , AHB , CHI , I2C , UART , SPI.

Guys you can go through these questions and definitely it will be helpful in cracking the VLSI job in the field of design and verification. These questions are asked to a candidate with 5 years of experience in Design and Verification. It will also be helpful for any fresher candidate.

You guys can get the answers of these questions by your own but I will be preparing the answers for these questionnaire in my next article.

Thank you very much guys . . Happy Learning . .

VKY Academy

Click Here for Design and Verification Interview Question Part-1

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