Post Views: 1 Part -1: Digital Fundamentals 1. How to design an AND gate using a 2×1 multiplexer?To implement an AND gate using a 2×1 multiplexer (MUX), follow these steps: The output of the MUX becomes:Y = A̅·0 + A·B = A·BHence, the MUX behaves like an AND gate. 2. Can a 2×1 multiplexer be […]
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Post Views: 6 Step 1 : RTL Design (Verilog for 2-bit Adder) RTL stands for Register Transfer Level. It’s a way of designing digital circuits — like processors, adders, or controllers — by describing how data moves between registers and what operations are performed on that data. module adder_2bit ( input [1:0] a, input [1:0]
Full VLSI Flow for a 2-bit Adder with DFT Verification Read More »
Post Views: 24 Shallow Copy:Copies only the reference to an object, not the actual object. Changes to one will affect the other. Deep Copy:Copies the entire object and its contents, creating an independent duplicate. Changes to one will not affect the other. Shallow Copy: Example class MyClass; int data; endclass module test; initial begin MyClass
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Post Views: 12 What is the difference between shallow copy and deep copy in System Verilog? Explain with an example. Write a System Verilog code to generate Fibonacci series. Write a System Verilog code to generate prime numbers from 1 to 50. Given an array with elements {50, 10, 0, 40, 20, 30}, write a
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Post Views: 19 Mailbox in SystemVerilog A mailbox in SystemVerilog is a communication mechanism used for passing data between different processes in a testbench environment. It allows processes to send and receive data asynchronously, making it a powerful tool for inter-thread communication. Why is Mailbox Used? What Technique Does Mailbox Use? Mailbox Methods in SystemVerilog
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Post Views: 21 Semaphore A semaphore in SystemVerilog is a synchronization mechanism used to control access to shared resources among multiple processes. It is particularly useful in testbenches to prevent race conditions when multiple threads try to access the same resource. A semaphore consists of a fixed number of keys (or tokens), which can be
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Post Views: 11 Preparing for an embedded engineering interview or examination can be challenging, given the technical depth and variety of topics covered. However, understanding and practicing the right set of questions can make a significant difference. Below, we delve into how these questions and answers are instrumental in preparing for interviews and exams, ensuring
Answers for the Embedded Engineer Interview Questions: Part-2 Read More »
Post Views: 30 1. What is a State Machine? What Are the Different Types? Explain the Difference? Which One is Most Preferable? A state machine is a sequential logic circuit that transitions between different states based on input signals and a predefined logic. It is used to model the behavior of digital systems. Types of
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Post Views: 6 The Graduate Aptitude Test in Engineering (GATE) is one of the most competitive exams for engineering students in India. To succeed, it’s essential to have a realistic and relatable strategy that aligns with the challenges students face. Below is a preparation plan that every student can connect with, tailored to both pre-final
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