# Design Verification Interview Question with Answer-Part-1

The overall interview process is divided into 3 parts:

The first part is Digital Logic design or Digital electronics concepts:

1. What is K – Map and why do we use it?

Answer: A Karnaugh Map (K-Map) is a graphical representation of truth tables used in digital design for simplifying Boolean algebra expressions. It helps in minimizing the number of terms in a Boolean expression and optimizing logical circuits.

2. What are the basic logic gates?

Answer: The basic logic gates are AND, OR, NOT, NAND, NOR, and XOR gates. These gates form the building blocks of digital circuits and are used to perform logical operations.

3. What are the universal logic gates?

Answer: Universal logic gates are types of logic gates that can be used to implement any other type of logic gate /logic circuit or logic equations. There are two primary universal logic gates: NAND gates and NOR gates.

NAND and NOR gates can be used to implement any type of logic gate or logic equation.

4. What is SOP and POS?

Answer: SOP (Sum of Products) and POS (Product of Sums) are two standard forms for representing Boolean expressions. SOP represents an expression as the sum of several product terms, while POS represents an expression as the product of several sum terms.

5. What are Minterm and Maxterm?

Answer: A minterm is a product term in which all variables appear in either true or complemented form. A maxterm is a sum term in which all variables appear in either true or complemented form.

6. What is the difference between Latch and Flipflop?

Answer: Latches and flip-flops are sequential circuits. The main difference is that a latch is level-sensitive and can change its output whenever the input changes, while a flip-flop is edge-triggered and changes its output only at the rising or falling edge of a clock signal.

7. What are Fan-in and Fan-out?

Answer: Fan-in refers to the number of input signals a gate or circuit can handle. Fan-out refers to the number of output signals a gate or circuit can drive without degradation of performance.

8. What are setup time and hold time?

Answer: Setup time is the minimum time before the clock edge that the input signal must be stable for proper operation of a flip-flop.

Hold time is the minimum time after the clock edge that the input signal must remain stable for proper operation.

1. What is the difference among Reg , Wire , Logic?

In SystemVerilog, the `reg`, `wire`, and `logic` data types are used to declare variables with different characteristics. Here’s a brief overview of the differences between them:

1. `reg` Data Type:
• Behavior: The `reg` data type represents a one-bit register. It is commonly used to model sequential logic elements such as flip-flops.
• Storage: It stores binary information (0 or 1) and is suitable for modeling individual bits in registers.
• Typical Use: Used in procedural blocks like always or initial blocks to model flip-flops or latch behavior.
• Example: `reg my_reg;`
2. `wire` Data Type:
• Behavior: The `wire` data type represents a one-dimensional net, connecting different logic elements. It is typically used to model combinational logic.
• Storage: It does not store a value but acts as a conduit for the flow of signals between different modules or blocks.
• Typical Use: Used to connect the outputs of combinational logic blocks and propagate signals between modules.
• Example: `wire my_wire;`
3. `logic` Data Type:
• Behavior: The `logic` data type represents a four-state logic value (`0`, `1`, `x`, or `z`). It is a more generalized data type that can represent multiple states, including unknown (`x`) and high-impedance (`z`).
• Storage: It is suitable for modeling digital logic values in a more general way and can be used for both sequential and combinational logic.
• Typical Use: Widely used in SystemVerilog for modeling digital logic circuits. Introduced to avoid the confusion between `reg` and `wire` in Verilog.
• Example: `logic [3:0] my_logic_vector;`

Note:

• In SystemVerilog, the use of `logic` is recommended over `reg` and `wire` for clarity and to avoid confusion, especially when dealing with vector types.
• `logic` is a more modern and versatile data type that encompasses the functionalities of both `reg` and `wire`.
• `logic` is introduced to address the limitations and ambiguities in the use of `reg` and `wire` in Verilog.

2. What is the difference between packed and unpacked array? with example.
Difference between packed and unpacked array:

Packed arrays are used for contiguous storage of bit or logic vectors, while unpacked arrays are used for storing elements of a complex data type like structures or other arrays. Example:

// Packed array
reg [7:0] packed_array [3:0];

// Unpacked array
reg [7:0] unpacked_array [3];

3. What is the difference between struct and union?

In Verilog/SystemVerilog, a struct is a composite data type that allows grouping of variables of different data types, while a union allows variables to share the same memory location, meaning only one of the members can be active at a time.
How to declare a dynamic array and how to add additional memory with the existing created memories?

4. How to declare a dynamic array and how to add additional memory with the existing created memories ?

Dynamic arrays are declared using the dynamic keyword in SystemVerilog. Memory can be added using the insert and delete methods. Example:
systemverilog
Copy code
int dynamic_array[]; // Declaration

dynamic_array.insert(42);
dynamic_array.insert(24);
Different types of constraints:

5. What are the different types of constraints?

In SystemVerilog, constraints are used to model and control the randomization of variables during simulation. They are commonly employed in verification environments to create realistic and varied test scenarios. Here are some different types of constraints in SystemVerilog:

Range Constraints:

Purpose: Restrict values to a specific range.
Example:

rand int my_variable;
constraint valid_range {
my_variable inside [0:255];
}

Weight Constraints:

Purpose: Assign weights to different constraint scenarios.
Example:

rand int my_variable;
constraint weighted_constraint {my_variable > 0 -> weight=2;}

Soft Constraints:

Purpose: Express preferences that do not have to be satisfied.
Example:

rand int my_variable;
constraint soft_constraint {
my_variable > 0 -> weight=2;
}

Functional Constraints:

Purpose: Define functional relationships between variables.
Example:

rand int var_a, var_b;
constraint functional_constraint {
var_a == var_b + 1;
}

Array Constraints:

Purpose: Apply constraints to arrays.
Example:

rand int my_array[5];
constraint array_constraint {
foreach (my_array[i]) my_array[i] > 0;
}

Implication Constraints:

Purpose: Define constraints based on logical implications.
Example:

constraint implication_constraint {
(condition_a && condition_b) -> my_variable == 42;
}

Distribution Constraints:

Purpose: Specify probability distributions for random variables.
Example:

rand int my_variable;
constraint distribution_constraint {
my_variable dist {10 := 20, 30 := 80, 100 := 5};
}

Disable Constraints:

Purpose: Temporarily disable certain constraints under specific conditions.
Example:

rand int my_variable;
constraint disable_constraint {
my_variable > 0;
disable iff (some_condition);
}

If-Else Constraints:

Purpose: Provide conditional constraints.
Example:

rand int var_a, var_b;
constraint if_else_constraint {
if (condition) var_a > var_b;
else var_a < var_b;
}

Complex Constraints:

Purpose: Combine multiple constraints to create more sophisticated scenarios.
Example:

rand int var_a, var_b;
constraint complex_constraint {
var_a > 0 && var_b < 100;
}

6. What are the difference between Soft Constraint and Hard Constraint?

Hard Constraints:

Definition: Hard constraints are strict conditions that must be satisfied during the randomization process. If a hard constraint is violated, the randomization fails, and the process is retried until a valid set of values meeting all hard constraints is found.
Effect of Violation: Violating a hard constraint results in a failure, and the SystemVerilog runtime system continues to attempt randomization until a valid solution is obtained.
Example:

rand int my_variable;
constraint hard_constraint {
my_variable > 0;
}
Soft Constraints:

Soft Constraint:

Definition: Soft constraints express preferences or priorities that influence the randomization process but are not strictly required. If a soft constraint is not satisfied, the randomization process continues, and the associated weight may influence the likelihood of certain scenarios being generated.
Effect of Violation: Violating a soft constraint does not lead to failure. The simulation continues, and the soft constraint’s weight affects the likelihood of certain scenarios.
Example:

rand int my_variable;
constraint soft_constraint {
my_variable > 0 -> weight=2;
}
Key Differences:

Failure Impact:

Hard Constraints: Violating a hard constraint leads to a failure, and the randomization process is retried until a valid solution is found.
Soft Constraints: Violating a soft constraint does not fail. The randomization process continues, and the soft constraint’s weight influences the likelihood of certain scenarios.
Retrying Randomization:

Hard Constraints: The SystemVerilog runtime system retries the randomization process until all hard constraints are satisfied.
Soft Constraints: The randomization process continues even if a soft constraint is not satisfied.
Weights:

Hard Constraints: Typically do not involve weights.
Soft Constraints: May include weights to influence the likelihood of certain scenarios.

7. What is callback?

A callback is a function or piece of code that is passed as an argument to another function and is executed after the completion of a certain task. It is a common programming pattern used for event handling.

8. What is forward declaration?

Forward declaration is a declaration of a variable, function, or class that tells the compiler that the entity exists but doesn’t provide the full details. It allows using the entity before its actual definition.
Where do we write assertions?

9. Where do we write assertions?

Assertions are written in the RTL (Register Transfer Level) code to specify properties or conditions that must hold true during simulation or synthesis. They are commonly used for design verification.
These concepts are fundamental to hardware description languages and programming in general, especially in the context of digital design and verification.

Questions asked from UVM domain for verification:

1. What is the difference between sequence and sequence item?

In UVM (Universal Verification Methodology), sequences, sequence items, sequencers, and TLM (Transaction Level Modeling) are key concepts used for creating modular and scalable testbenches. Here’s an overview of each:

Sequence vs. Sequence Item:

Sequence:

A sequence is a unit of work that encapsulates a series of transactions or operations to be executed in a testbench.
Sequences define the high-level behavior of a test, representing a sequence of operations that a testbench component (like a driver) should perform.
Sequences are typically derived from the uvm_sequence class.
Sequence Item:

A sequence item is an individual transaction or data structure that is part of a sequence.
Sequence items carry the data that needs to be transmitted or processed during the execution of a sequence.
Sequence items are typically derived from the uvm_sequence_item class.
Example:

class my_sequence extends uvm_sequence;
`uvm_object_utils(my_sequence)

my_sequence_item item1, item2;

function new(string name = “my_sequence”);
super.new(name);
endfunction

// Construct and randomize sequence items
item1 = my_sequence_item::type_id::create(“item1”);
item2 = my_sequence_item::type_id::create(“item2”);

``````// Perform operations using sequence items
start_item(item1);
finish_item(item1);

start_item(item2);
finish_item(item2);``````

endclass

2. what is sequencer ?

Sequencer in UVM:

A sequencer is responsible for controlling the flow of sequences and sequence items in a testbench.

The sequencer receives requests from the test (via a driver) to execute specific sequences.

UVM sequencers are derived from the uvm_sequencer class.

Sequencers manage the distribution of sequence items to the appropriate driver for further processing.

Example:

class my_sequencer extends uvm_sequencer #(my_sequence_item);
`uvm_component_utils(my_sequencer)

function new(string name = “my_sequencer”, uvm_component parent = null);
super.new(name, parent);
endfunction
endclass

3. What is TLM?

TLM (Transaction Level Modeling) in UVM:

TLM in UVM refers to the abstraction of communication between different components in a testbench using transactions.

Transactions encapsulate the data being exchanged between components, enabling a higher level of abstraction and reusability.

TLM helps in separating the functional aspects of the design from the verification environment.

Example:

class my_transaction extends uvm_sequence_item;
`uvm_object_utils(my_transaction)

int data;

function new(string name = “my_transaction”);
super.new(name);
endfunction
endclass

In UVM, TLM is often used in conjunction with sequences and sequence items to model transactions at a higher level of abstraction. TLM is employed for communication between different components in a testbench, facilitating modular and reusable verification environments.

Happy Learning . . .

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