Junior Research Fellow

Malaviya National Institute of Technology Jaipur Department of Computer Science and Engineering

Applications are invited for the temporary posts of Junior Research Fellow (JRF) for SERB, DST, Govt. of India, Project “SWARD -Secure next-generation Wireless Access RaDio technology for smart cities in India” in the Department of Computer Science and Engineering. The desirable minimum essential and desirable qualifications for the project posts are as follows.

Interested candidates should submit their resume highlighting

1) Essential Educational Qualifications – Year of passing, percentage, board/university, examination passed (from X and XII onwards)

2) Address of communication, phone number, mobile number (if any) and email address.

3) Professional Experience and one professional reference not related.

4) Familiarity with Programming Languages

5) Hardware Proficiency The essential and desirable qualifications for the project associates are as follows:


Junior Research Fellow (DST-SWARD-RBB):

One Number Rs.31000/= per month + 16% HRA initially for one year extendable up to the end of the project on a yearly basis

Essential qualification

Minimum Qualifications: B.E./B.Tech. in Computer Science and Engg./ Computer Engg./ Information Technology/ Communication and Computer Engg./ Electronics and Communication Engg. M.E./M.Tech. in Computer Science and Engg./ Computer Engg./ Software Engg./ Information Technology/ Information Security/ VLSI with first class. GATE qualification, The candidates will be required to handle lab work of latest Networking environment and work in embedded/IoT systems laboratory. The candidate shall be exposed to handling the labs and will be encouraged to contribute in research work related to the project. The selected candidates shall be encouraged to register to PhD/already registered candidates can also apply.

Important Dates:

Submission of application on prescribed format through email or by post May 08, 2019 till May 22, 2019

No separate interview letter shall be sent for the shortlisted candidates. They will be informed through their email ID and also by phone. Information shall be communication dates May 23-24, 2019

Date of Test/Interview/Presentation May 30, 2019

Click here to apply :

Leave a Comment

Your email address will not be published. Required fields are marked *

The US Hits China With a Huge Microchip Bill FPGA Design Engineer Interview Questions Semiconductor Industry the huge break through