Post Views: 4 Step 1 : RTL Design (Verilog for 2-bit Adder) RTL stands for Register Transfer Level. It’s a way of designing digital circuits — like processors, adders, or controllers — by describing how data moves between registers and what operations are performed on that data. module adder_2bit ( input [1:0] a, input [1:0] […]
Full VLSI Flow for a 2-bit Adder with DFT Verification Read More »
Post Views: 16 Mailbox in SystemVerilog A mailbox in SystemVerilog is a communication mechanism used for passing data between different processes in a testbench environment. It allows processes to send and receive data asynchronously, making it a powerful tool for inter-thread communication. Why is Mailbox Used? What Technique Does Mailbox Use? Mailbox Methods in SystemVerilog
Mailbox in System Verilog Read More »
Post Views: 33 Testing a VLSI (Very Large Scale Integration) design block is a multistep process aimed at ensuring its functionality and performance. The testing process involves the following key steps: Pre-silicon Verification: Before fabrication, the design undergoes extensive simulation using tools such as Verilog or VHDL simulators. This step helps identify and rectify design
How to Test a VLSI Design Block? Read More »
Post Views: 17 Pre-silicon verification is a vital aspect of VLSI (Very Large Scale Integration) design, involving the validation of a design before its physical fabrication. This step is crucial for ensuring that the design functions correctly and meets its specified requirements. Pre-silicon verification typically includes extensive simulation and analysis using specialized tools and methodologies.
SoC/IP Pre-silicon verification of VLSI Design Read More »
Post Views: 50 The overall interview process is divided into 3 parts: The first part is Digital Logic design or Digital electronics concepts: Answer: A Karnaugh Map (K-Map) is a graphical representation of truth tables used in digital design for simplifying Boolean algebra expressions. It helps in minimizing the number of terms in a Boolean
Design Verification Interview Question with Answer-Part-1 Read More »
Post Views: 66 Job Code : JR42302 Intern – Design Verification Location : Hyderabad , Telangana Eligibility: Job Description : The Intern – Design Verification in the Non-Volatile Memory Group at Micron Technology, Inc., will be a core technical individual contributor in the design and verification of the on-chip controller and mixed-signal circuitry in NAND
VLSI Design Verification Internship @Micron Technology Hyderabad Read More »
Post Views: 19 Registration Start Date 02-11-2023 Registration End Date 30-11-2023 Type – Open ChallengeDisplay – Flagship EventsVenue – Online Event Electropreneur Park-Bhubaneswar, an ESDM CoE of Software Technolgy Parks of India with support from the Electronics & IT Department, Govt. of Odisha, Odisha Computer Application Centre (OCAC), IESA, Synopsis, and Industry Partners, is organising
Odisha Semiconductor Design Challenge (Last Date: 30-11-2023) Read More »
Post Views: 50 This is the second part of Embedded Engineer Interview series. These questions are also helpful for the aspirant who are preparing for their semester examination of UG or PG.
Embedded Engineer Interview Questions: Part-2 Read More »
Post Views: 104 The following set of questions will be helpful for the Embedded Engineer interview preparation. These questions will also be helpful for semester exam preparation.
Embedded Engineer Interview Questions:Part-1 Read More »
Post Views: 88 The semiconductor industry has become an integral part of nearly every sector, playing a critical role in shaping how efficiently and intelligently we live. From powering the tiniest electronic devices to enabling advanced technologies, semiconductors form the backbone of modern innovation. India has emerged as a global hub for semiconductor design, producing
List of Leading VLSI Companies in India: Websites, Type, and City-Wise List Read More »
