Post Views: 691 ELECTRICAL OVERSTRESS Electrical Overstress (EOS) is a term refers to failures caused by the application of excessive voltages or currents to a component. Electrical overstress is a phenomenon where electrical signals applied to a circuit or a device exceeds normal operating parameters. These excessive electrical signals are abnormal by definition and are […]
mechanisms in Integrated circuits Read More »
Post Views: 24,093 OBJECTIVE: The objective of this lab is to learn the Virtuoso tool as well as learn the flow of the Full Custom IC design cycle and Standard Cell Layout Design. You will finish the lab by running DRC, LVS and Parasitic Extraction on the various designs. In the process, you will create
INTRODUCTION TO CADENCE EDA TOOL SUIT Read More »
Post Views: 935 The objective of conducting the summer internship courses is to Provide conceptual clarity on the topics covered and understand various techniques of problem-solving through guided learning. Expose the students to various tools that are available and prepare them to design and implement innovative projects through industry-oriented mentor support. Enable the students to
Summer Internship-2020 @ Silicon Institute of Technology, Bhubaneswar (Odisha) Read More »
Post Views: 20,591 NITMGH/ES/SERB-DST/CY/33/2019-20/1556 Dated: 13-11-2019 Motivated and eligible candidates are invited for a walk-in-interview for the position of Junior Research Fellow (JRF) for the project entitled “Assessment of climate change impact on soils and various water basins of Meghalaya using existing and newer techniques” under under the HICAB (Network Programmes) as part of the National Mission on
JUNIOR RESEARCH FELLOW (JRF) UNDER DST SPONSORED PROJECT (NIT Meghalaya) Read More »
Post Views: 754 On behalf of the University Grants Commission (UGC), the National Eligibility Test (NET) is conducted for determining the eligibility of Indian nationals for the Eligibility for Assistant Professor only or Junior Research Fellowship & Assistant Professor Both, in Indian Universities and Colleges. Till June 2018, the CBSE conducted the NET in 84
UGC NET -December 2019 Download Admit Card Read More »
Post Views: 1,055 Location: India, Bangalore Job Details: Job Description: This is an exciting role in a new team in Intel India. The Quartus Validation Engineer focuses on validating PSG’s FPGA design software and ensuring OS compatibility, dedicated to improving the quality and user experience of our FPGA design software. Responsibilities:Develop automation plans to support new
FPGA Software Validation Engineer – Intern@Intel Read More »
Post Views: 915 Development of GPGPU based parallel algorithms for land cover classification of remotely sensed big data Selection Procedure Walk-in-interview Walk-in-interview date and time 30 October 2019 at 10:00 a.m. Essential Qualifications i) M.E/M. Tech or equivalent degree in Computer science/Electrical engineering/Electronics/Information Technology, or M.Sc in Statistics/Mathematics/Physics/Electronics/Computer Science, or MCA.ii) Good knowledge in computer
Jobs @ ISI (Indian Statistical Institute), Kolkata (West Bengal) Read More »
Post Views: 718 Important Dates: Opening date for online application : 01st October 2019 Last date for submission of online application : 07th November 2019 11:00 PM Tenure: Not below three weeks and not exceeding four weeks during Winter Vacations of IIT Bhubaneswar (Winter Vacation of the institute: 26.11.2019 to 31.12.2019). The student registered for a degree in
Internship Programme for winter-2019 @ IIT Bhubaneswar Read More »
Post Views: 19,951 In Digital ELectronics there are various laws and rules for the simplification of boolean functions which are basically used to minimize the complexity of digital hardware design by minimizing the boolean function. “De Morgan’s Theorems of Laws” is one of the most powerful theorems used in digital electronics for the minimization of
De Morgan’s Theorems of Boolean Algebra [Digital Electronics] Read More »
