What is the difference between shallow copy and deep copy in System Verilog? Explain with an example.
Write a System Verilog code to generate Fibonacci series.
Write a System Verilog code to generate prime numbers from 1 to 50.
Given an array with elements {50, 10, 0, 40, 20, 30}, write a System Verilog code to print the array in descending order.
If functional coverage is 100% and code coverage is 50%, is it acceptable to close the project? What about the reverse scenario?
What is the difference between issuing a write and precharge at the same time versus issuing a write followed by precharge? Which one is logically correct? If both have some significance explain ?
What is the difference between pre-silicon and post-silicon validation? What types of faults cannot be rectified in post-silicon and must be verified during pre-silicon?
Explain the concept of polymorphism in System Verilog with a simple example.
What is the difference between ATPG and MBIST?
Related posts:
Design Verification Interview Question with Answer-Part-1
Mailbox in System Verilog
Solutions of FPGA Design Engineer Interview Question Part-1
Semaphore in System Verilog
SoC/IP Pre-silicon verification of VLSI Design
Design Verification Interview Question Part-2
Introduction to System Verilog
Introduction to Verilog