system verilog

Design Verification Interview Question with Answer-Part-1

Post Views: 13 The overall interview process is divided into 3 parts: The first part is Digital Logic design or Digital electronics concepts: Answer: A Karnaugh Map (K-Map) is a graphical representation of truth tables used in digital design for simplifying Boolean algebra expressions. It helps in minimizing the number of terms in a Boolean …

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Design and Verification Engineers @First Pass Semiconductors

Post Views: 747 Requirements BE/B.Tech /ME/M.Tech 2 years to 15 years Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment. Define and execute a detailed verification plan from spec working with architects, designers, system engineers. Write tests, Debug tests, automate regression …

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Senior Android Developer@Asiczen Technologies, Bhubaneswar [Urgent Requirement]

Post Views: 19,853 Job Description: We are looking for a passionate senior Android/IOS Developer who can push mobile technologies to its limits. This developer shall work with our team of talented engineers to design and build the next generation IoT products that are going to set new standards in technology. Education/Industry Experience:  Bachelors/Masters degree …

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Senior Verification Engineer @Asiczen Technologies [Urgent requirement] Basically ETC/ECE/EC/EEE/CSE

Post Views: 952 Location: Bhubaneswar, Bangalore, Delhi, Mumbai, Hyderabad Job Description: Responsible for feature list development and development of the verification plan.Able to individually contribute to the development of testbench and test case development.Responsible for writing required documentation on test benches and/or test plans.Responsible for debugging the design and follow-ups till resolution.Able to own and …

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The US Hits China With a Huge Microchip Bill FPGA Design Engineer Interview Questions Semiconductor Industry the huge break through